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4-mbit (256k x 16) static ram cy62146e mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-07970 rev. *c revised may 4, 2007 features ? very high speed: 45 ns ? wide voltage range: 4.5v?5.5v ? ultra low standby power ? typical standby current: 1 a ? maximum standby current: 7 a ? ultra low active power ? typical active current: 2 ma @ f = 1 mhz ? easy memory expansion with ce and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? offered in pb-free 44-pin tsop ii package functional description [1] the cy62146e is a high performance cmos static ram organized as 256k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high). the input and output pins (io 0 through io 15 ) are placed in a high impedance state when: ? deselected (ce high) ? outputs are disabled (oe high) ? both byte high enable and byte low enable are disabled (bhe , ble high) ? when the write operation is active (ce low and we low) to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ) is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 9 for a complete description of read and write modes. logic block diagram 256k x 16 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble a 17 note 1. for best practice recommendations, refer to the cypress application note an1064, sram system guidelines. [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 2 of 11 pin configurations the figure that follows shows the 44-pin tsop ii pinout. [2] product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max cy62146ell ind?l/auto-a 4.5 5.0 5.5 45 ns 2 2.5 15 20 1 7 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 15 a 16 a 8 a 9 a 10 a 11 a 13 a 14 a 12 oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss nc 10 a 17 top view notes 2. nc pins are not connected on the die. 3. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25. [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 3 of 11 maximum ratings exceeding maximum ratings may sh orten the battery life of the device. user guidelines are not tested. storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with power applied .......... .............. .............. ..... ?55c to + 125c supply voltage to ground potential ............................... ?0.5v to + 6v (v ccmax + 0.5v) dc voltage applied to outputs in high-z state [4, 5] ....................?0.5v to 6v (v ccmax + 0.5v) dc input voltage [4, 5] ............... ?0.5v to 6v (v cc max + 0.5v) output current into outputs (low) ............................ 20 ma static discharge voltage ........ ........... ............ ........... >2001v (mil-std-883, method 3015) latch up current...................................................... >200 ma operating range device range ambient temperature v cc [6] cy62146ell ind?l/auto-a ?40c to +85c 4.5v to 5.5v electrical characteristics over the operating range parameter description test conditions 45 ns (ind?l/auto-a) unit min typ [3] max v oh output high voltage i oh = ?1.0 ma 2.4 v v ol output low voltage i ol = 2.1 ma 0.4 v v ih input high voltage v cc = 4.5v to 5.5v 2.2 v cc + 0.3 v v il input low voltage v cc = 4.5v to 5.5v ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels 15 20 ma f = 1 mhz 2 2.5 i sb2 [7] automatic ce power down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = v cc(max) 17 a capacitance for all packages. tested initially and after any design or process changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions tsop ii package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 77 c/w jc thermal resistance (junction to case) 13 c/w notes 4. v il(min) = ?2.0v for pulse durations less than 20 ns for i < 30 ma. 5. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 6. full device ac operations are based on a minimum of 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 7. only chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 4 of 11 ac test loads and waveforms figure 1. ac test load and waveforms parameters 5.0v unit r1 1800 ? r2 990 ? r th 639 ? v th 1.77 v data retention characteristics over the operating range parameter description conditions min typ [3] max unit v dr v cc for data retention 2 v i ccdr [7] data retention current v cc = 2v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v ind?l/auto-a 1 7 a t cdr [8] chip deselect to data retention time 0ns t r [9] operation recovery time t rc ns data retention waveform [10] figure 2. data retention waveform 3v v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time= 1 v/ns fall time= 1 v/ns output v all input pulses r th r1 equivalent to: thevenin equivalent v cc(min) v cc(min) t cdr v dr > 2.0v data retention mode t r v cc ce or bhe .ble notes 8. tested initially and after any design or proce ss changes that may affect these parameters. 9. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 10. bhe . ble is the and of bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling bhe and ble . [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 5 of 11 switching characteristics over the operating range [11, 12] parameter description 45 ns (ind?l/auto-a) unit min max read cycle t rc read cycle time 45 ns t aa address to data valid 45 ns t oha data hold from address change 10 ns t ace ce low to data valid 45 ns t doe oe low to data valid 22 ns t lzoe oe low to low-z [13] 5ns t hzoe oe high to high-z [13, 14] 18 ns t lzce ce low to low-z [13] 10 ns t hzce ce high to high-z [13, 14] 18 ns t pu ce low to power up 0ns t pd ce high to power down 45 ns t dbe ble /bhe low to data valid 22 ns t lzbe ble /bhe low to low [13] 5ns t hzbe ble /bhe high to high-z [13, 14] 18 ns write cycle [15] t wc write cycle time 45 ns t sce ce low to write end 35 ns t aw address setup to write end 35 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 35 ns t bw ble /bhe low to write end 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [13, 14] 18 ns t lzwe we high to low-z [13] 10 ns notes 11. test conditions for all parameters other than tri-state parame ters are based on signal transition time of 3 ns (1v/ns) or le ss, timing reference levels of 1.5v, input pulse levels of 0 to 3v, and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 12. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 13. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the output enters a high impedence state. 15. the internal memory write time is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write. [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 6 of 11 switching waveforms read cycle no. 1 (address transition controlled) [16, 17] figure 3. read cycle no. 1 read cycle no. 2 (oe controlled) [17, 18] figure 4. read cycle no. 2 previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 16. the device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 17. we is high for read cycle. 18. address valid before or similar to ce and bhe , ble transition low. [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 7 of 11 write cycle no. 1 (we controlled) [15, 19, 20] figure 5. write cycle no. 1 write cycle no. 2 (ce controlled) [15, 19, 20] figure 6. write cycle no. 2 switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 21 t bw t sce data io address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data io oe bhe /ble note 21 notes 19. data io is high impedance if oe = v ih . 20. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 21. during this period, the ios are in output state. do not apply input signals. [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 8 of 11 write cycle no. 3 (we controlled, oe low) [20] figure 7. write cycle no. 3 write cycle no. 4 (bhe /ble controlled, oe low) [20] figure 8. write cycle no. 4 switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 21 ce address we data io bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 21 data io address ce we bhe /ble [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 9 of 11 truth table ce we oe bhe ble inputs outputs mode power hxxxxhigh-z deselect/power downstandby (i sb ) l x x h h high-z output disabled active (i cc ) lhllldata out (io 0 ?io 15 ) read active (i cc ) l h l h l data out (io 0 ?io 7 ); io 8 ?io 15 in high-z read active (i cc ) l h l l h data out (io 8 ?io 15 ); io 0 ?io 7 in high-z read active (i cc ) l h h l l high-z output disabled active (i cc ) l h h h l high-z output disabled active (i cc ) l h h l h high-z output disabled active (i cc ) l l x l l data in (io 0 ?io 15 ) write active (i cc ) l l x h l data in (io 0 ?io 7 ); io 8 ?io 15 in high-z write active (i cc ) l l x l h data in (io 8 ?io 15 ); io 0 ?io 7 in high-z write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 cy62146ell-45zsxi 51-85087 44-pin thin smal l outline package ii (pb-free) industrial 45 CY62146ELL-45ZSXA 51-85087 44-pin thin small outline package ii (pb-free) automotive-a contact your local cypress sales repres entative for availability of these parts. [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 10 of 11 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram figure 9. 44-pin tsop ii, 51-85087 mobl is a registered trademark, and more battery life is a tr ademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. max min. dimension in mm (inch) 11.938 (0.470) plane seating pin 1 i.d. 44 1 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) ejector pin r g o k e a x s 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) base plane 0.10 (.004) 22 23 top view bottom view 51-85087-*a [+] feedback [+] feedback
cy62146e mobl ? document #: 001-07970 rev. *c page 11 of 11 document history page document title: cy62146e mobl ? , 4-mbit (256k x 16) static ram document number: 001-07970 rev. ecn no. issue date orig. of change description of change ** 463213 see ecn nxr new data sheet *a 684343 see ecn vkn added preliminary automotive-a information updated ordering information table *b 925501 see ecn vkn added footnote #8 related to i sb2 and i ccdr added footnote #13 related ac timing parameters *c 1045260 see ecn vkn converted automotive-a specs from preliminary to final [+] feedback [+] feedback

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